The present invention relates to a digital duty cycle correction circuit of a Delay Locked Loop (DLL).
In general, in DDR SDRAM, the input and output operations of data are performed at the rising and falling edges of a clock in synchronization with an external clock. The data output by the read operation must be identical to the timing of the rising and falling edges of an external clock. Therefore, it is required that a circuit within the DDR SDRAM receive the external clock and control the output of the data by generating an internal clock that is delayed for a given time. The circuit generating the internal clock includes a DLL or a Phase Locked Loop (PLL). Furthermore, although the ratio of a duty high pulse and a duty low pulse of an external input clock is distorted when the DLL or PLL is used, the signal retention ratio is satisfactory when the duty cycle of the output of the data is 0.5. Accordingly, circuits exceeding DDR2 necessarily require a Duty Cycle Corrector (DCC) circuit for sensing the duty of an external clock and making the duty cycle of a clock controlling the output of the data at the time of the output 0.5.
FIG. 1 is a schematic block diagram of a conventional DLL. The DLL 100 includes an input buffer 101, a global control unit 102, a first delay unit 110, a second delay unit 120, an ECDL controller 103, a mode generator 104, a delay control unit 105, a phase control unit 130, a DCC controller 106, a dummy output buffer 107 and an output buffer 108. The first delay unit 110 further includes a first phase detector 111, a first coarse delay unit 112, a first fine delay unit 113 and a first replica 114. The second delay unit 120 further includes a second phase detector 121, a second coarse delay unit 122, a second fine delay unit 123 and a second replica 124. The phase control unit 130 includes a first DCC phase mixer 131, a second DCC phase mixer 132 and a third phase detector 133.
The DCC are available in analog and in digital. The analog DCC circuit is high in accuracy, but is difficult to implement for high-speed operation, whereas the digital DCC circuit is easy to implement for high-speed operation, but occupies a large area and has high power consumption.